Michael McNamara

technology, networking, virtualization and IP telephony

Ethernet Routing Switch 8600 Software Release v5.1.3.1

by

Avaya has released v5.1.3.1 software for the Ethernet Routing Switch 8600/8800. This release addresses a single issue;

  • 8692 CP boards with the new PCMCIA controller could experience high cpu utilization and other systemic effects while accessing certain types of PCMCIA cards. The problem has now been addressed. (wi00564790)

Please review the release notes for any additional information.

Cheers!

Upgrading DPC FPGA firmware on 8683XLR

by

I upgraded an Ethernet Routing Switch 8606 over the weekend from v5.1.1.0 software to v5.1.3.0 software. As the switch booted the v5.1.3.0 software I was alerted that I needed to upgrade the DPC FPGA firmware on the 8648GTR and 8683XLR blades that were in the chassis. You’ll notice too that the switch was also complaining that I had not yet formatted the PCMCIA card since I upgrade to the 5.1.x software stream.

Copyright (c) 2010 Avaya, Inc.
CPU Slot 5:    PPC 745 Map B
Version:       5.1.3.0/020
Creation Time: Aug  5 2010, 19:19:09
Hardware Time: SEP 13 2010, 15:51:09 UTC
Memory Size:   0x10000000
Start Type:    cold
SMART MODULAR TECH. HYA ATA

The /pcmcia device mounted successfully, but it appears
to have been formatted with pre-Release5.1 file system code.
Nortel recommends backing up the files from /pcmcia, and
executing dos-format /pcmcia to bring the file system on the
/pcmcia device to the latest ERS8600 baseline.
open_file:can't open "/pcmcia/pcmboot.cfg" 0x380003 _dosFsLib_FILE_NOT_FOUND
/flash/  - Volume is OK

Loaded boot configuration from file /flash/boot.cfg
Attaching network interface lo0... done.

Press  to stop auto-boot...
Loading /flash/p80a5130.img ... 12637154 to 43802740 (43802740)
Starting at 0x1000000...

SMART MODULAR TECH. HYA ATA
 Booting PMC280 Mezz HW. Please wait.......
The BootCode address is 0xe100100 3303
.
Mezz taking over console and modem.....
Mezz CPU Booted successfully

Initializing backplane net with anchor at 0x4100... done.
Backplane anchor at 0x4100... ..
Mounting /flash: .done.
CPU5 [09/13/10 11:52:36] SW INFO Found serial number <11:22:33:44:55:66> in file
CPU5 [09/13/10 11:52:36] SW INFO License Successfully Loaded From License Type -- ADVANCED

Ethernet Routing Switch 8600  System Software Release 5.1.3.0
Copyright (c) 1996-2010 Avaya, Inc.

CPU5 [09/13/10 11:52:36] SW INFO System boot
Warning: Please save your configuration after boot-up to avoid
CPU5 [09/13/10 11:52:36] SW INFO ERS System Software Release 5.1.3.0
CPU5 [09/13/10 11:52:40] MPLS INFO All MPLS components are up and active
CPU5 [09/13/10 11:52:40] HW INFO Card inserted: Slot=5 Type=8692SF
CPU5 [09/13/10 11:52:40] SW INFO R-Module inserted: Slot=1 Type=8630GBR, waiting to bootup...
CPU5 [09/13/10 11:52:40] SW INFO R-Module inserted: Slot=3 Type=8683XLR, waiting to bootup...
CPU5 [09/13/10 11:52:40] HW INFO Initializing 8692SF in slot #5 ...
CPU5 [09/13/10 11:52:49] SW INFO Slot  1: Loading /flash/p80j5130.dld
CPU5 [09/13/10 11:52:49] SW INFO Slot  3: Loading /flash/p80j5130.dld
CPU5 [09/13/10 11:53:28] SW INFO Slot  3: 8683XLR Initializing.  Do not remove board.
CPU5 [09/13/10 11:53:29] SW INFO Slot  1: 8630GBR Initializing.  Do not remove board.
CPU5 [09/13/10 11:53:33] SW INFO Slot  3: 8683XLR Initialization completed.
CPU5 [09/13/10 11:53:34] SW INFO Slot  3: Restart new image version 5.1.3.0
CPU5 [09/13/10 11:53:34] SW INFO Slot  1: 8630GBR Initialization completed.
CPU5 [09/13/10 11:53:34] SW INFO Slot  1: Restart new image version 5.1.3.0
CPU5 [09/13/10 11:53:43] SW INFO Slot  3: Loading /flash/p80j5130.dld
CPU5 [09/13/10 11:53:44] SW INFO Slot  1: Loading /flash/p80j5130.dld
CPU5 [09/13/10 11:54:04] SW INFO slot 1 found NP heartbeat - R-Module is online
CPU5 [09/13/10 11:54:04] SW WARNING Slot 1 is running older software version(s) of FPGA. Please upgrade to the latest version(s)
CPU5 [09/13/10 11:54:04] SW WARNING DPC FPGA current revision: 184. Upgrade to the latest revision: 194
CPU5 [09/13/10 11:54:08] SW INFO slot 3 found NP heartbeat - R-Module is online
CPU5 [09/13/10 11:54:08] HW INFO Initializing 8630GBR in slot #1 ...
CPU5 [09/13/10 11:54:08] SW WARNING Slot 3 is running older software version(s) of FPGA. Please upgrade to the latest version(s)
CPU5 [09/13/10 11:54:08] SW WARNING DPC FPGA current revision: 184. Upgrade to the latest revision: 194
CPU5 [09/13/10 11:54:09] HW INFO Initializing 8683XLR in slot #3 ...

*****************************************************************
* Copyright (c) 2010 Avaya, Inc.
* All Rights Reserved
* Ethernet Routing Switch 8006
* Software Release 5.1.3.0 (Released - General Availability)
*****************************************************************
Login: CPU5 [09/13/10 11:54:10] SW INFO Loading configuration from /flash/config.cfg
CPU5 [09/13/10 11:54:10] SW INFO NTP Enabled
CPU5 [09/13/10 11:54:10] SNMP INFO VRF name: GlobalRouter (VRF id 0): Max route warning set
CPU5 [09/13/10 11:54:10] SW INFO The system is ready
CPU5 [09/13/10 11:54:10] SNMP INFO Booted with PRIMARY boot image source - /flash/p80a5130.img
CPU5 [09/13/10 11:54:12] SW INFO PCMCIA card detected in Master CPU "ERS-8606" slot 5, Chassis S/N SS11111111
CPU5 [09/13/10 11:54:12] IP INFO the OSPF Md5 key file does not exist
CPU5 [09/13/10 11:54:12] SNMP INFO Chassis with Power Supply redundancy
CPU5 [09/13/10 11:54:12] SNMP INFO Fan Up(FanId=1, OperStatus=2)
CPU5 [09/13/10 11:55:00] SNMP INFO Sending Cold-Start Trap

I needed to copy down the software from the TFTP server to the local /flash member;

ERS-8606:5# copy 10.1.1.1:dpc194.xsvf /flash/dpc194.xsvf

With the software on the flash we can now start the upgrade;

ERS-8606:5# config diag fpga dpc update 1 /flash/dpc194.xsvf
Found /flash/dpc194.xsvf

WARNING: Starting the FPGA update process. DO NOT reset the card or  box during
this process. Please wait for FPGA UPDATE SUCCESS message. (Command prompt will
 be returned but update process will take several minutes)
This Message will get appended to the log file upon completion of the update.
The command prompt will return after the upgrade is complete.                                                

CPU5 [09/13/10 12:02:41] COP-SW INFO Slot 1: FPGA UPDATE SUCCESS - You will need to reboot the switch or re-insert/reset the slot for FPGA to take effect.

You’ll need to reboot the switch in order for the module(s) to load the new FPGA firmware.

Cheers!

Avaya ERS8600 Planning and Engineering Network Design

by

Avaya has released an updated version of it’s Ethernet Routing Switch 8600 Planning and Engineering Network Design document. The document, NN46205-200, Rev 02.02, was originally released with the 5.1 software release for the Ethernet Routing Switch 8600. The document has been updated to include some of the features and changes incorporated into the software since the document was originally published.

There’s a lot of great technical information in this document including a lot of recommendations and best practices.

Cheers!

Ethernet Routing Switch 8600 Software Release v5.1.3.0

by

Avaya has released v5.1.3.0 software for the Ethernet Routing Switch 8600.

Please review the release notes for all the resolved issues, known issues and known limitations.

Switch management

  • The command “show ports stats show-all” was previously not displaying all of the associated port statistics information. The ERS 8600 now will display the proper information. (Q02012952-01)
  • The egress queue service rates configured in NNCLI mode were previously getting lost after a reboot. The egress queue service rates configured are now retained after a reboot. (Q02116358)
  • In NNCLI mode “show qos egress-queue-set <queue-set-id>” command was showing no output. ERS 8600 now displays the proper output on executing this command. (Q02116618)
  • Initiating a traceroute via JDM to an unknown destination while other ping or traceroute activities were being performed simultaneously from the same switch could potentially lead to system instability. This has been corrected. (Q02137566)

Platform

  • In specific scenarios with filters and port mirroring being used simultaneously, the ERS8600 will no longer see an increase in CPU utilization due to packets being sent to the CP/SF incorrectly. (Q02141867)
  • In some specific ACL configurations with a default-action specified, the ERS8600 previously blocked certain traffic patterns improperly. The issue has been addressed. (Q02068243)
  • Previously links on an R-module could stay up for 60 seconds when the primary SF/CPU (of a dual non-HA SF/CPU configuration only) was not properly removed (module pulled out without prior master reset or switchover). The ERS 8600 now ensures that the links are brought down immediately when the primary SF/CPU is removed for this configuration. (Q02102654)
  • The radius secret key will now be stored as encrypted in the shadov.txt file. Before upgrading to 5.1.3.0, it is now required of the user to delete the radius secret key and then re-add it after the up-grade is complete to avoid accessibility problem with RADIUS. This situation has already been addressed in 7.0.0.0 code release. (Q01881817-03)
  • When multiple failovers are performed on an ERS 8600 in HA environments, some R module I/O modules could come back up off-line. This situation is now addressed in the 5.1.3.0 code release but also requires the use of the new updated DPC FPGA image (see File Names section). Associated with this 5.1.3.0 Release, the DPC firmware image must be upgraded for all R-module I/O modules to the dpc194.xsvf firmware image. If the firmware image is not upgraded, the user will receive a warning log message upon any re-boot of 5.1.3.0 code release, warning them that DPC FPGA firmware image is out of revision. (Q02053766-01)
  • On E/M module cards, receiving 802.3x pause frames on gigabit Ethernet ports could previously result in port level resets. (Q02101087)
  • For an ERS 8600 running with 8692 SF/CPU with SuperMezz, the SuperMezz physical LED will now display properly. (Q02102364)
  • During boot-up, the potential for 8612XLRS 10Gig port flapping will no longer occur. (Q02138423)
  • An error in loading configuration file previously resulted in all of the line cards being disabled. This behavior was added in 5.1 code. This behavior is now changed such that the rest of the correct config will be loaded and all the remaining line cards will not be disabled, but only the line card associated with the improper configuration will be disabled. This situation is different than an “invalid config file, with verify-config flag enabled”, in which case the system will not load the config and will bring up the system with all I/O modules disabled (versus loading the default config). This situation has already been addressed in 7.0.0.0 code release. (Q02056382-01)
  • A power usage calculation error has been corrected for 8648TXE and 8691SF cards which previously lead to improper warnings being generated in some configurations indicating that the chassis was running on low power. (Q02072016)
  • The value of the ingress records was showing improper values via the command show ip mroute-hw resource usage. This has been now been addressed and the proper values for these records are now displayed. (Q02120442)
  • The software power tables embedded in the ERS 8600 were out of sync with the Power Supply Calculator posted via the web. This inconsistency has now been addressed. This issue has already been addressed in 7.0.0.0 code release. (Q02020261-01)

RSTP/MSTP

  • An outage of 30sec has been observed in some RSTP setups when one of the root ports was disabled. This issue has now been addressed and the ERS 8600 re-converges within the proper time interval. (Q01984762-02)
  • In RSTP mode, the log file transfer feature was not working properly. This issue has been addressed and the log file transfer feature is now working as expected when RSTP mode is enabled. (Q02101565-01)

IP Unicast

BGP

  • In a specific aggregation scenario, when an ERS 8600 forms a neighbour relationship with Cisco, the BGP session will no longer go down due to a malformed AS path. (Q02085844-01)
  • During some specific BGP transition scenarios, system instability was previously seen for the ERS 8600. This issue is now addressed. (Q02134841)
  • BGP instabilities are no longer observed associated with a HA failover. (Q02135118)
  • After an HA failover with a BGP route policy enabled, some BGP routes could be rejected and not re-advertised by the ERS 8600. This issue has been addressed. (Q02136224)

OSPF

  • After an upgrade it is now ensured that the OSPF MD5 keys are no longer lost. (Q02127996)

VRRP

  • Enabling and then disabling the IST protocol will no longer lead to improper values displayed in the VRRP records. (Q02106080-01)

IP Multicast

  • ERS 8600 now ensures that when an IP Multicast sender and the receiver are connected to the same ERS 8600, that SPM (Source Path Messages – specific message type within PGM) packets are no longer dropped. This is independent of PGM being enabled or not, as PGM packet flows can function with PIM-SM enabled. (Q02119454)

MLT / SMLT

  • ERS8600 will now deterministically (and properly) hash traffic flows for IPVPN Lite traffic on MLT links. (Q02142913)
  • MLTs will now come up properly when the LACP Min Link feature is enabled. (Q02034692-02)
  • In some rare network events, it is possible to learn the fdb-entry for an IP interface of an SMLT peer on the SMLT associated port instead of the IST MLT. In this scenario, the fdb-entry will now be properly updated afterward to correctly point to the IST MLT. (Q02142730)
  • CPU high buffer utilization and associated IST instabilities will no longer be observed in specific high CPU and high traffic load conditions for the ERS 8600. (Q02109963)
  • The 8632TXE module will now properly go offline in the scenario where both master and slave CPU’s are removed in systems running with smlt-on-single-cp enabled. (Q02123052)

VLACP

  • If a mismatching VLACP configuration exists on two ends of a connection associated with a SLT, the SLT will no longer show as SMLT up improperly after a reboot. (Q02119095)

BFD

  • On an ERS8600 running both BGP and BFD, when one tries to enable BGP first and then BFD on the BGP neighbour, the BFD related config can now be set properly. (Q02141063)

Cheers!

Avaya Technical Configuration Guide for BGP

by

I use BGP extensively to provide dynamic routing between a number of vendors, business partners and affiliated organizations with whom I’m multi-homed to. I recently had to determine if Nortel/Avaya supported eBGP MultiHop on the Ethernet Routing Switch 8600 software release 5.x (they do). Thankfully I was able to peer with a Cisco 6500 switch that was sitting behind a Cisco firewall module from an Ethernet Routing Switch 8600 without any significant issues,.

If you are looking for a great resource on BGP I would highly recommend O’Reilly’s book titled BGP.

If you are looking for Avaya/Nortel specific information concerning their BGP implement then you are in luck. Avaya has a technical configuration guide for the ERS 8600 that focuses on BGP. While this is an older document (November 2007) it still does a great job of providing a number of configuration examples and explaining the basics.

In the near future I might need to use an ERS 8606 as an Internet router. I’ll need to peer with the ISP since I’m multi-home to independent Internet Service Providers, although I’m not sure if the 8692SF can handle a full BGP routing table. Has anyone ever tried to feeding a full (or partial) BGP routing table from the Internet to an ERS 8800/8600 switch?

Cheers!

Recent Posts

Categories

SUBSCRIBE BY EMAIL